| 摘要 |
PURPOSE:To stabilize the PLL which generates a clock synchronously with a horizontal synchronizing pulse of the HDTV system. CONSTITUTION:A 2nd loop in which a phase of an output signal of a digital VCO 7 and a phase of a reference signal are compared by an analog phase comparator 4, an analog VCO 12 is controlled in response to the comparison output and an output of the analog VCO 12 is fed to a clock terminal of the digital VCO 7 is provided to the PLL circuit in addition to a 1st loop, in which a phase of an input signal and a phase of a signal based on an output signal of the digital VCO 7 are compared by the digital phase comparator 4 and the digital VCO 7 is controlled by the comparison output. Thus, the PLL is equivalent to the operation as the digital PLL, the operation is made stable and a different clock is not required for the digital circuit. |
