| 摘要 |
PURPOSE:To realize the clock recovery circuit not using a clock with a high frequency. CONSTITUTION:A reference data clock from a reference data clock generating section 7 is divided into N by a delay section 8, each divided clock is delayed and N sets of clock signals with a different phase are generated. A selection section 9 selects a clock signal with a least phase difference from that of the digital data among the said N sets of clock signals based on an average lead or lag signal from a sequential filter 2 and outputs the selected signal as a data clock. |
