Integrated semiconductor DRAM with cells with word and bit lines - has data bus coupled to first driver circuit via write switch for data input signal amplifying

摘要

Each internal read-out amplifier (SA) is coupled to a pair (BLP) of bit lines and has two outputs. There is at least one pair of data bus lines (DB,DB), and switches (BS) for coupling to amplifier outputs. One bus (DB) is coupled to first driver circuit (DVR-WR) via a write switch (T-WR) for amplifying a data input signal (DI) in write mode. The other data bus (DB) is coupled to a second driver circuit (DRV,RD) for amplifying a datum, resulting in read out mode. The first driver circuit input is linked to a line carrying the data input signal. The second driver circuit output is coupled to a line carrying a data output signal (DO) via a read-out switch (T-RD). ADVANTAGE - Low-cost, compact design, taking up less space on semiconductor chip.