发明名称 |
Erasable programmable read only memory |
摘要 |
A read only semiconductor memory includes a memory cell matrix including a number of floating-gate type erasable programmable memory cells. A column selector being connected between a plurality of column lines of the memory cell matrix and a writing circuit and a sense amplifier. A column decoder has a plurality of outputs each being connected through a corresponding transfer gate to the column selector and also being pulled up to a high voltage. A row decoder has a plurality of outputs each being outputted through a corresponding transfer gate to a corresponding one of row lines of memory cell matrix and also being pulled up to a high voltage to the outputs of the row decoder. Each of the transfer gates is formed of an enhancement type or a substrate-VT type field effect transistor. A control circuit including a pump-up circuit receives a control signal for supplying a gate voltage signal to gates of all the field effect transistors.
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申请公布号 |
US5198998(A) |
申请公布日期 |
1993.03.30 |
申请号 |
US19910729557 |
申请日期 |
1991.07.15 |
申请人 |
NEC CORPORATION |
发明人 |
KOBATAKE, HIROYUKI |
分类号 |
G11C17/00;G11C16/06;G11C16/08;H01L21/8247;H01L27/115;H01L29/788;H01L29/792 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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