发明名称 |
Data processing system with address translation function for different page sizes. |
摘要 |
<p>The data processing system translates a logical address made up of a partial space number, a logical space number and an address within a page to a physical address made up of a physical page number and the address within a page and accesses a memory section under the coexistence of a plurality of page sizes. The system further comprises a table holding section for holding a plurality of sets of copies of a plurality of address translation tables stored in the memory section on a partial space basis. The plurality of sets of copies are each assigned to a particular page size. A load control section loads one of the plurality of address translation tables into the table holding section in response to an address translation table load command. A directory supervising section supervises partial spaces each corresponding to one of the plurality of address translation tables held in the table holding section. A first loading section executes by defining the partial spaces assigned to the same page size as a single supervisory unit in the directory supervising section, load control over the plurality of address translation tables independently. This data processing system is capable of translating addresses having a plurality of page sizes dynamically to thereby enhance efficient use of a memory and improve the overhead of an operating system. <IMAGE></p> |
申请公布号 |
EP0533190(A2) |
申请公布日期 |
1993.03.24 |
申请号 |
EP19920116015 |
申请日期 |
1992.09.18 |
申请人 |
NEC CORPORATION |
发明人 |
FUJIWARA, YOSHIFUMI;KATO, HIROSHI |
分类号 |
G06F12/10 |
主分类号 |
G06F12/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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