| 发明名称 |
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| 摘要 |
An intergrated circuit processing method comprises the formation on a substrate (10) of a metallised conductor pattern (11). A layer of insulating material (12) is formed over the conductor pattern and a mask (14) is superimposed thereon. The mask is resistant to plasma etching and is provided at predetermined positions with apertures (15) defining required void outlines. Plasma etching through the mask forms vias (16) in the insulating layer (12) which communicate with the metallised conductor pattern (11). The mask (14) is removed to leave the integrated circuit with communicating vias (16) which enable connection to the conductor pattern (11). |
| 申请公布号 |
JPH0519818(B2) |
申请公布日期 |
1993.03.17 |
| 申请号 |
JP19840068946 |
申请日期 |
1984.04.06 |
| 申请人 |
PURETSUSHII SEMIKONDAKUTAAZU LTD |
发明人 |
SUCHIIBUN JEEMUSU ROODESU |
| 分类号 |
H01L21/302;H01L21/3065;H01L21/768;H01L23/522 |
主分类号 |
H01L21/302 |
| 代理机构 |
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