WORD-LINE STRUCTURE OF MEMORY ARRAY

摘要

The twisted word line for preventing the scramble of signal transmission in a memory array comprises a polysilicon layer (GP) connected to the gate of a MOS transistor and arranged parallel with one another, and a low resistance of metal layer (ME) coupled to the polysilicon layer. The memory array includes a number of cells having MOS transistors and capacitors, a number of bit lines and a number of word lines. The metal layer (ME1) of first word line (WL1) is twisted at least one time with the metal layer (ME2) of second word line (WL2) adjacent to the first word line (WL1). The polysilicon lines (GP1-GP4) and metal lines (ME1-ME4) are coupled through contact regions (C1,C2,C3,C4).