发明名称 PRECEDING ONE DETECTING CIRCUIT AND FLOATING POINT ADDER-SUBTRACTOR
摘要 PURPOSE:To simultaneously proceed the prediction of a cancelling amount and the subtraction of a mantissa by predicting the cancelling amount at the time of subtracting the mantissa which is generated when the difference of an exponent value is + or -,1 or 0, in a floating point adder-subtractor. CONSTITUTION:A minuend Xk and a subtrahend Yk are used so as to generate a redundant binary numeral Zsd in a redundant binary numeral generating circuit 101. Next, the redundant binary numerals Zsd(and Zsd k+j of the k-th(k is a natural number) digit and the (k+1)-th digit from low order are used so as to generate intermediate carry C(and an intermediate sum Sk in accordance with a formula Zsdk=2Ck+Sk so that Ck=2sdk is adopted at the time of Zsdk+1=1 or -1 and Ck=0 is adopted at the time of 2sdk+1=0 in an intermediate sum and intermediate carry generating circuit 102. A scan value generating circuit 103 generates scan value Zk by intermediate carry Ck-1 and the intermediate sum Sk from low order so that Zk=0 is adopted at the time of Ck-1+Sk=0 and Zk=1 is adopted at the time of the formula except Ck-1+Sk=0. The position of one at the highest order of Zk, order becomes the position which is equal to the highest significant digit position or the one digit higher position at the time of subtracting.
申请公布号 JPH0553765(A) 申请公布日期 1993.03.05
申请号 JP19920015601 申请日期 1992.01.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MIYOSHI AKIRA;TANIGUCHI TAKASHI
分类号 G06F7/00;G06F7/485;G06F7/49;G06F7/50;G06F7/74 主分类号 G06F7/00
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