发明名称 Vector locked loop.
摘要 <p>A vector locked loop (10) is disclosed having a topology somewhat similar to two cross coupled phase locked loops, but wherein both magnitude and phase are used as feedback signals. The output signal is generated by combining the outputs of two VCOs (12, 14) in a combiner network (20). This output signal is fed back to the input, where phase and magnitude detectors (34, 38) are used to generate error signals. These error signals are processed (39) to yield control signals for controlling the frequencies of the two VCOs. The vector locked loop can be adapted for a number of applications, including frequency translation, modulation (phase, amplitude or arbitrary), and high efficiency linear power amplification. &lt;IMAGE&gt;</p>
申请公布号 EP0529874(A1) 申请公布日期 1993.03.03
申请号 EP19920307363 申请日期 1992.08.12
申请人 HEWLETT-PACKARD COMPANY 发明人 DASILVA, MARCUS K.
分类号 H03L5/00;H03C1/06;H03D3/24;H03F1/32;H03L7/07;H03L7/08;H03L7/087;H03L7/093 主分类号 H03L5/00
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