| 摘要 |
<p>PURPOSE:To accurately and stably fetch a reference clock signal even when a high speed clock is used by installing a signal combination detecting circuit and signal holding/outputting circuit. CONSTITUTION:This clock synchronizing circuit and signal processor are equipped with a signal combination detecting circuit 11 and a signal holding/ outputting circuit 12. Further, when a combination of signal states that both a first clock signal phiR with a frequency of Fr and a second clock signal H with a frequency of Fh which is n times frequency Fr of the first clock signal phiR become 'H' level is detected by signal combination detecting circuit 11, state result signal SET is output as a combined state of 'H' levels of both signals O and (-) to signal holding/outputting circuit 12. Further, clock output signal phiOUT with a frequency of Fr that is synchronous with the second clock signal phiH based on the second clock signal phiH and the state result signal SET is outputted from the signal holding/outputting circuit 12.</p> |
