| 摘要 |
PURPOSE:To reduce a leakage current of a load transistor of a memory cell and prevent deterioration of a gate withstand voltage and to improve reliability in a stacked complete CMOS type static RAM. CONSTITUTION:Channel regions 19, 22 and drain regions 23, 20 of load transistors Q3, Q4 formed of p-channel TFTs, are superposed through gate insulating films. The region 19 and the region 20 of the transistor Q3 are extended reversely to each other at a contact hole C9 as a branch point, and the regions 22, 23 of the transistor Q4 extended substantially reversely to each other at a contact hole C8 as a branch point. |
