RAPIDLY CONVERGING PHASE-LOCKED LOOP WITH A QUADRANT SENSITIVE PHASE STEP SIZE

摘要

"HIGH SPEED HALF DUPLEX MODEM WITH FAST TURNAROUND PROTOCOL" A phase locked loop circuit which eliminates the phase difference between an incoming reference signal and a sampling signal by sampling the incoming reference signal to produce a sampled signal. The sign of the sampled signal at two sample points is compared to determine in which quadrant a predetermined one of these sample points is located. The phase adjustment to the sampling signal is dependent upon the quadrant in which this sample point is located and the magnitude of this sample point. A large phase difference produces a large phase adjustment so that this sample point is quickly locked onto the zero-crossing points of the incoming reference signal. A small phase difference produces a small phase adjustment and prevents jitter. The lock onto the zero-crossing point of the incoming reference signal minimizes the data error rate of the modem.