发明名称 CLOCK GENERATING CIRCUIT
摘要 <p>PURPOSE:To always obtain a stable clock at the time when a video signal cannot be obtained and the video signal is restored. CONSTITUTION:The phase of the synchronizing signal in an input video signal and that of a feedback clock are compared with each other by a phase comparing means (second phase comparing circuit) 5 of a phase synchronizing circuit 3, and the output of this phase comparing means 5 is held at a certain value by a holding means (sampling and holding circuit) 12 at the time of drop-out, and the feedback clock is synchronized with the synchronizing signal by control means (an input signal detecting circuit 13 and a counter control circuit 14) at the time of restoration from drop-out.</p>
申请公布号 JPH0530478(A) 申请公布日期 1993.02.05
申请号 JP19910203811 申请日期 1991.07.18
申请人 CANON INC 发明人 OWADA MITSURU;AIDA AKIRA;YAMASHITA NOBUITSU
分类号 H04L7/027;H04N5/06;H04N5/10;H04N5/95;H04N5/956 主分类号 H04L7/027
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