发明名称 REGULATING CIRCUIT FOR PHASE DIFFERENCE BETWEEN CLOCK SIGNALS
摘要 PURPOSE:To regulate a phase difference between a basic clock signal and an inspection clock signal automatically and thereby to make it possible to output a regulated clock signal being matched in a phase with the basic clock signal. CONSTITUTION:A clock phase difference detecting circuit 7 which receives a basic clock signal 1 and a regulated clock signal 6 as inputs and outputs a motor control signal 8, a delay circuit 3 which receives an inspection clock signal 2 and a delay gate selection signal 10 as inputs and outputs the regulated clock signal 6, and a stepping motor 9 which receives the motor control signal 8 as an input, outputs the delay gate selection signal 10 and operates synchronously with the basic clock signal 1, are provided.
申请公布号 JPH0526923(A) 申请公布日期 1993.02.05
申请号 JP19910181466 申请日期 1991.07.23
申请人 NEC CORP;KOUFU NIPPON DENKI KK 发明人 KIJINO TAKESHI;TACHIBANA YOSHIMI
分类号 G01R25/00;H02P8/00;H02P8/14 主分类号 G01R25/00
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