| 摘要 |
<p>A circuit arrangement for generating the clock signal of a predetermined frequency f(UART) for a smart card interface, the interface being used for transferring data from a smart card to a device e.g. a mobile telephone at a predetermined data rate f(D). Using a phase-locked loop (PLL) and a number of programmable counters (N1-N4), the output of the circuit i.e. the smart card interface clock signal can have a frequency f(UART) which is a multiple of the data rate. In particular, the counters (N1-N4) and phase-locked loop (PLL) can be chosen so that f(UART) is sixteen times f(D) which allows a Universal Asynchronous Receiver Transmitter circuit to be used in the interface. <IMAGE></p> |
