| 摘要 |
In an analog-to-digital converter, one-bit A/D conversion stages are connected in series to receive an analog signal. Each conversion stage includes a sample-and-hold circuit for sampling an analog signal from a preceding stage, a comparator for comparing it with a specified voltage level to produce a logic signal at one of two discrete levels depending on whether the signal received from the preceding stage is higher or lower than the specified level. The signal received from the preceding stage is summed with a prescribed reference voltage of one of opposite polarities depending on the level of the logic signal to produce an analog output signal. The successive conversion stages are driven so that the analog signal from each stage is transferred to the next, and the logic signals generated by the individual conversion stages are delayed so that they appear simultaneously at digital output terminals. <IMAGE> |
