| 摘要 |
<p>PURPOSE:To minimize the rise in an average speed and a peak speed of a VC by excluding a 1st idle cell period after a period position and discharging it so as to apply control of using the idle cell period as a start point of a succeeding period position. CONSTITUTION:An FIFO 80 has a write address generating circuit 81, a memory 82 and a read address generating circuit 83 and stores only a real cell in response to a cell write control signal 91, an input cell 92, a cell read control signal 93, and a clock 95 and outputs an output cell 94 and an empty signal 96. A control means 10 eliminates an idle cell block coming at first after a period position being an integral number of multiple of a cell phase in the cell write control signal 91 representing the presence of the arrived real cell to the FIFO 80. Furthermore, a cell read control signal 93 is subject to on/off control in response to the state of the real cell and remaining idle cells to suppress properly the increase in the cell stream. That is, since the time compression of the cell stream is relaxed, the rise in the average speed and the peak speed is decreased.</p> |
