| 摘要 |
PURPOSE:To suppress the omission of a picture at the time of performing a reduction processing and the loss of the smoothness of the picture at the time of performing an expansion processing. CONSTITUTION:A block 401 having a value of n-128 and a block 402 having a value of n which compose a main scanning direction arithmetic part are inputted in a selector 403. The selector 403 outputs the value of the block 401 when a reduction/expansion signal to the S terminal is Low and outputs the value of the block 402 when the signal is High. A selector 409 inputs values from adders 407, 408, and outputs the value of the adder 407 when the carry of the adder 408 is 0 and outputs the value of the adder 408 when the carry is 1. The output of this selector 409 is inputted to an 8-bit latch 410. A block 411 has an initial value of the positional relation of the picture element before converting and the picture element after converting. A select signal to a selector 412 generates a line synchronizing signal by a flip flop 413 by delaying it by a picture element. |
