| 摘要 |
PURPOSE:To obtain a bypass scan path where a propagation time of data is short, concentration of wiring prevents a chip area from being increased, and furthermore the number of pins is not increased. CONSTITUTION:A plurality of bypass scan paths 4a-4d are inserted between an SI terminal 31 and an SO terminal 32 in serial, thus constituting a scan path for propagating serial data. In each of the bypass scan paths 4a-4d, a selection data propagation retention register 44 and a mode data propagation retention register 45 are placed on the bypass path which is formed by a bypass wire 42. Therefore, the selection data propagation retention register 44 and the mode data propagation retention register 45 do not perform any useless shift operation in the bypass scan path where the register path is selected when a test data and a test result data are propagated, thus enabling time for performing shift-in of the test data and that for performing shift-out operation of the test result data to be reduced. |
