| 摘要 |
PURPOSE:To simplify the circuit constitution of a high speed signal portion, to reduce power consumption, to make the size small and to reduce the cost by devising the transmitter so that the synchronization processing at a high speed is not required. CONSTITUTION:Plural channel data with equal bit rate are inputted in parallel to parallel/serial conversion shift register 21 at a sender side. A sent serial data is given to a serial parallel conversion shift register 22 and a latch circuit 23 at a receiver side, in which they are converted into parallel data of plural channels, a synchronization pattern detection circuit 24 detects a synchronization pattern detection circuit 24 in the plural channels and each channel number is related to an original channel number at the sender side and the result is outputted from a channel exchange matrix 26. |
