SCAN CONVERTER CONTROL CIRCUIT HAVING MEMORIES AND ADDRESS GENERATOR FOR GENERATING ZIGZAG ADDRESS SIGNAL SUPPLIED TO THE MEMORIES

摘要

A scan converter control circuit includes first and second memories (111, 112) each having a data write mode and a data read mode which are selected in response to a switching signal so that the first memory is in the data write mode when the second memory is in the data read mode and the first memory is in the data read mode when the second memory is in the data write mode. A write address counter (12) generates a write address which is to be alternately supplied to the first and second memories and generates a write completion signal when the write address becomes equal to a predetermined count value. A read address counter (13) generates a read address which is to be alternately supplied to the first and second memories and generates a read completion signal when the read address becomes equal to a predetermined count value. A data input controller (14) enables the write address counter in response to a data input signal supplied from an external circuit and disables the write address counter when receiving the write completion signal. A memory switching controller (15) generates the switching signal having a logic value which is changed in response to the write completion signal. A data output controller (16) enables the read address counter in response to the write completion signal and disables the read address counter in response to the read completion signal.