发明名称 |
DESIGNATED FAIL NUMBER ADDRESS SEARCH CIRCUIT OF MEMORY TESTER |
摘要 |
PURPOSE:To search an X-address or a Y-address having a fail address more than a prescribed value as a relief address in short time. CONSTITUTION:A memory 2 stores fail data in the same address as the fail address of a memory for tested object. The memory 2 is read at high speed by an address signal from an address generator 1. A comparator 4 adds fail data which is read from the memory 2 as to the same X-address or the same Y-address and compares an added value with the prescribed value stored in a register 3. The comparator 4 outputs a write enable signal to a memory 5 when the added value of fail data is large. The memory 5 stores the address signal outputted from the address generator 1 as data at timing when the write enable signal is inputted. |
申请公布号 |
JPH04330700(A) |
申请公布日期 |
1992.11.18 |
申请号 |
JP19910099914 |
申请日期 |
1991.05.01 |
申请人 |
HITACHI ELECTRON ENG CO LTD |
发明人 |
UCHIDA YOSHIO |
分类号 |
G01R31/28;G06F11/22;G11C29/00;G11C29/44 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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