发明名称 PROGRAMMABLE DELAY LINE
摘要 PURPOSE:To easily and quickly attain the output of an input signal by delaying accurately this signal for an optional time through a simple circuit. CONSTITUTION:A counter 11 divides a reference clock into plural pieces and outputs plural types of clocks of different intervals. A multiplexer 5 selects and outputs a specific one of those clocks with a selective signal. Then the input signals are successively shifted and outputted through a shift register 12 synchronously with the clocks outputted from the multiplexer 5.
申请公布号 JPH04319812(A) 申请公布日期 1992.11.10
申请号 JP19910112165 申请日期 1991.04.18
申请人 MITSUBISHI ELECTRIC CORP 发明人 SAKANE YOSUKE
分类号 H03K5/135 主分类号 H03K5/135
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