| 摘要 |
A computer architecture and method capable of retaining data after a system clock has been halted to conserve power. The computer comprises first processing circuitry, the first circuitry comprising dynamic components. The dynamic components include such devices as intermediate pipeline registers, arithmetic logic units, address generators, and instruction decode and control circuitry. The computer further comprises second processing circuitry, the second circuitry comprising static components. In a preferred embodiment, the static components comprise instruction registers, stop controls, general purpose registers, status registers, and random access memory. The use of dynamic components in the architecture of a preferred embodiment maximizes cost and size considerations, while the static components allows instruction execution and the system clock to be halted. The combination of dynamic and static components preserves information which enables the system to resume execution after the system clock has been stopped without data loss. This architecture reduces power consumption compared to a system implemented entirely in dynamic logic, while minimizing cost and area. Methods are also provided to stop this architecture and restart it without data loss. |
