| 摘要 |
PURPOSE:To decrease the hardware quantity by providing an adding means, an addition result selecting circuit, and a parity selecting circuit. CONSTITUTION:Signal lines 55, 46 from adding circuits 42, 43 are inputted to adding circuits 40, 41. That is to say, a carry in case a carry of the lowest rank to the upper rank from the lower rank is '0' and '1' is sent out. To signal lines 57, 58 inputted to the adding circuits 42, 43, signals 10, 01 are inputted in advance. To addition result selecting circuits 44, 45 from signal lines 60, 64, 62 and 66, the upper rank and the lower rank of an addition result in case a carry of the lowest rank is '1' are inputted, the upper rank and the lower rank of an addition result in case a carry of the lowest rank is '0' are inputted, an actual carry is inputted from signal lines 67, 68, and from signal lines 69, 70, an actual addition result is selected and outputted. A parity selecting circuit 48 inputs a parity to an addition result of a double length in case when a carry of the lowest rank is '0' and '1', from signal lines 73, 75, inputs an actual carry from the signal line 75, and selects and outputs an actual parity from a signal line 76. |
