| 摘要 |
<p>PURPOSE:To obtain a system clock generating circuit where it is unnecessary to raise the frequency of an external clock at the time of the rise of the frequency of a system clock. CONSTITUTION:Inverting amplifiers 11 to 14 connected in odd columns cascade connection constitute a ring oscillator 10, and control inputs 111, 121, 131, and 141 to control the delay times of inverting amplifiers 11 to 14 are provided to control the oscillation frequency. A phase comparator 20 to which the output of the ring oscillator 10 and the external clock are inputted, an LPF 30, and the ring oscillator 10 constitute a PLL, and a prescribed output of inverting amplifiers 11 to 14 of the ring oscillator 10 is obtained as the clock output.</p> |
