| 摘要 |
PURPOSE:To shorten the propagation time, and to improve the operation speed. CONSTITUTION:The adder is provided with an exclusive OR circuit 11 for outputting exclusive OR EO1 of addition numbers A, B, an exclusive NOT OR circuit 12 for outputting exclusive NOT OR ENO1 of the addition numbers A, By a multiplexer 13 for inputting EO1 and ENO1, and outputting EO1 and ENO1 as MX1, when the addition number C is '1', and the addition number C is '0', respectively, a multiplexer 14 for inputting EO1 and ENO1, and outputting EO1 and ENO1 as MX2, when the addition number C is '0', and when the addition number C is '1', respectively, an exclusive OR circuit 16 for outputting exclusive OR EO2 of addition numbers D, E, a multiplexer 15 for outputting MX2 and MX1 as a sum bit S, when EO2 is '1', and when EO2 is '0', respectively, a carry bit generating circuit 17 for inputting the addition numbers A, B and C and outputting a carry bit CO1, and a carry bit generating circuit 18 for inputting the addition numbers D, E and MX2 and outputting a carry bit CO2. |
