发明名称 |
POSITION ALIGNMENT METHOD OF SEMICONDUCTOR WAFER |
摘要 |
<p>PURPOSE:To obtain a mask position alignment method which is not affected by the random position errors of chips arranged on a wafer and the position deviation errors caused by spin coat of resist, metal evaporation, etc. CONSTITUTION:An approximation formula of each chip position is deviated in which statistical processing like a method of least squares is applied to mark position detected values in the respective chips arranged on a wafer and the random error components are eliminated. Chip intervals are obtained from the values of the wafer center part of the above approximation formula. By using said intervals as scales, the subsequent mask alignment is performed.</p> |
申请公布号 |
JPH04271109(A) |
申请公布日期 |
1992.09.28 |
申请号 |
JP19910000898 |
申请日期 |
1991.01.09 |
申请人 |
HITACHI LTD;HITACHI KEISOKUKI SAABISU KK |
发明人 |
SUGIYAMA HIDEJI;SASE YOSHIMITSU;KONISHI IWAO;KITAHAMA TATSUYA |
分类号 |
G03F1/00;G03F9/00;H01L21/027;H01L21/30 |
主分类号 |
G03F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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