Geometric arrangement for single gate multi-source and drain FET - comprises central insulated gate surrounded by concentric ring of individually isolated source and drain regions

摘要

The single gate, multi-source/drain field effect transistor comprises a highly-doped segmented toroidal (or square-plan) diffusion region (contg. at least three segments) set within a substrate of a second doping type and covered with an insulating oxide layer. Each segment (G1 to G8) is isolated (ISO) from adjoining segments and features an individual source (S1,S2) or drain (D1 to D5) contact formed from a metallic layer (K) inset into the oxide insulator. The central gate contact (GE) overlaps the inner edge of each segment (AD1,AD2,AS2) and completely covers the central channel region (KG). ADVANTAGE - Unique geometric arrangement allows size of source and drain areas and channel resistance to be defined in relation to one another.