| 摘要 |
<p>A memory cell array divided type multi-port memory device having random access circuit and serial access circuit, including: a plurality of cell array sections (14A-14D) each having a plurality of memory cells (C) disposed in a matrix form, the plurality of cell array sections (14A-14D) being disposed in a column direction at a predetermined pitch, each the cell array section (14A-14D) having a plurality of word lines (WL) and bit lines (BL), the word lines (WL) being connected to the memory cells (C) disposed in a row direction for selection of the connected memory cells (C), and the bit lines (BL) being connected to the memory cells (C) disposed in a column direction for data transfer to and from the selected memory cells (C); a row decoder (RD) for activating a desired one of the word lines (WL); sense amplifier (13A-13D) provided for each the bit line (BL) for sensing data read out to each the bit line (BL); a RAM port connected to the bit lines (BL) via RAM transfer gates; a column decoder (12AB, 12CD) for selectively turn on/off the RAM transfer gates; a plurality of data transfer lines (A) each having a data transfer gate (TRG1, TRG2) at the intermediate position thereof, the data transfer lines (A) being connected to the bit lines (BL) and formed on a layer different from layers of the word lines (WL) and bit lines (BL); data transfer gate control means (TGC) for turning on/off a desired one of the data transfer gates (TRG1, TRG2); a plurality of serial registers (15) connected to the data transfer lines (A); a serial port (SQ) connected via each serial transfer gate to each the serial register (15); and a serial decoder (16) for serially turning on/off the serial transfer gates. <IMAGE></p> |
