| 摘要 |
PURPOSE:To output a synchronized reception signal by setting the extent of delay in accordance with phase relations among a reception-side clock, a reference frame, and the reception signal at the time of the start of transmission of a digital signal from a transmission circuit to a reception circuit. CONSTITUTION:A programmable delay circuit 21 has delay lines connected in series in 30 stages, and a delay extent control circuit 24 takes out two signals in accordance with the extent of delay to be successively varied and set. A digital signal discriminating circuit 63 discriminates these two signals at the timing synchronized with the reference clock supplied from a clock frame phase source 65. A discrimination timing detecting circuit 22 fetches two discriminated output signals and decides whether two output signals are kept in the matched state within a prescribed time or not and reports the result to the circuit 24. After the extent of delay is settled by the circuit 24, it is transmitted to a transmission circuit 10, and switching to a signal source 51 is performed, and a reception circuit 20 discriminates the signal to be transmitted synchronously with the clock and the frame phase. |
