发明名称 |
Gold interconnect with sidewall-spacers |
摘要 |
In an integrated circuit, gold interconnect metal lines are electroplated onto plating (Pd) and barrier (TiW) layers, using patterned photoresist. The photoresist is stripped and the plating layer portions thus exposed are etched to expose field areas of the barrier layer. Next, sidewall spacers are formed along each side of the interconnect lines. The field areas of the barrier layer are then etched to isolate the gold interconnect lines. The spacers offset the amount of undercut due to isotropic etching of the TiW barrier metal layer. After etching, the sidewall spacers serve to preserve the as-deposited profile of the gold interconnect lines against breadloafing in a subsequent annealing step.
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申请公布号 |
US5145571(A) |
申请公布日期 |
1992.09.08 |
申请号 |
US19900562265 |
申请日期 |
1990.08.03 |
申请人 |
BIPOLAR INTEGRATED TECHNOLOGY, INC. |
发明人 |
LANE, RICHARD H.;EBEL, TIMOTHY M. |
分类号 |
H01L21/768;H01L23/532 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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