| 摘要 |
The apparatus detects and displayes the state of a processor not using an emulator. The apparatus includes a processor (300) for generating system clock signal, reset signal, and machine cycle signal, for executing instructions according to wait signal, for executing instructions according to wait signal by fetch cycle units and for accessing and outputting address signal and data, a display (400) connected to data and address ports of the processor to display the data and address, a switch (SW) for starting operation of the processor, an operating command unit (100) for generating operating command signal synchronized to system clock signal, and a stand-by signal generating unit (200) for generating a standby signal.
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