| 摘要 |
PURPOSE:To shorten an execution time by transferring a data signal, supplied from a register, not through an arithmetic part. CONSTITUTION:The instruction decoding circuit 103 of a control part 101 decodes an instruction read out of a memory 105 to specify two of registers 111-119, and supplies a signal indicating the data of the registers to buses 121 and 123. The instruction for the arithmetic part 125 is sent to the arithmetic part 125, which processes the data supplied to the buses 121 and 123 and then outputs a signal indicating the arithmetic result to a bus 129. Selectors 141-149 selects the signals of the buses 121 and 129. Thus, the arithmetic unit is provided with the transfer bus 121 and selectors 141-149 which can transfer the data not through the arithmetic part 125, and then the transfer and arithmetic accompanied by the transfer such as postpositioned arithmetic are carried out in one cycle at the same time to shorten the execution time. |
