发明名称 SAMPLING CIRCUIT FOR ANALOG SIGNAL
摘要 PURPOSE:To enable signal sampling at the moment when a trigger signal is generated, by correcting trigger timing corresponding to the phase delay of an input signal due to passage via low-pass filtering circuit. CONSTITUTION:An analog signal detected by detector 1 has a disused frequency component removed by active LPF3 and is sampled by sample holding circuit 4. A sampling signal applied to this circuit 4 from trigger pulse generating circuit 6 is corrected in terms of time delay by trigger timing correcting circuit 7 corresponding to the phase delay due to LPF3. Therefore, the input signal value at the moment when a sampling pulse is generated is sampled, so that accurate measurements by A/D conversion, etc., can be take.
申请公布号 JPS56111433(A) 申请公布日期 1981.09.03
申请号 JP19800015255 申请日期 1980.02.08
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HATAYAMA JIYUNICHI;OONO YOSHIHIRO;MATSUBA TETSUO
分类号 G01J1/44;H03K7/02 主分类号 G01J1/44
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