| 摘要 |
A digital signal processor (DSP) makes a conditional judgment based on a value held in a flag register in accordance with the result of an arithmetic operation, selectively outputs data representing either a predetermined value or "0" in accordance with the result of the decision, adds the value of the output data to a value held in a coefficient memory address register, and holds the resultant value in the address register. Accordingly, in executing pipeline processing, a read address of the coefficient data memory can be directly designated without altering the flow of a program, thus shortening the processing speed and facilitating the programming.
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