| 摘要 |
PURPOSE:To receive data without fail while allowing its phase fluctuation when the phase of the data from other data transmitter-receiver has large fluctuation. CONSTITUTION:Input data (a) are normally latched at a fall point of a clock signal (e) in a flip-flop (FF)1. When the large phase fluctuation occurs in the input data (a) while a FF7 is reset, the phase of the input clock (a) itself also largely fluctuates, the simultaneous occurrence of the differentiation result from respective differentiation circuits 2 and 3 is detected in a gate 6 and the FF7 is inversed. As a result, a inversed clock (i) can be obtained as the new clock signal (e) instead of an input clock (b) from a selector 4. |
