| 摘要 |
PURPOSE:To remove a noise by providing a multi-stage sampling control part to sample plural number of stages by a clock signal for sampling an input signal, and taking the logical product of the output signal of each state. CONSTITUTION:The subject circuit consists of a four-state sampling control part 4 to sample the input signal 1 by the clock signal 2 of optional frequency and a noise removing signal generating and control part 5 to take the logical product of its output signals. The four-stage sampling control part 4 is provided with four flip flops 31 to 34, and samples the input signal as synchronizing with the rise of the clock signal 2. Further, the noise removing signal generating and control part 5 is provided with an AND gate 6 and a delay gate 7 to delay the output signal of the FF 34, and the AND gate 6 takes the logical product of the signals of the FFs 31 to 33 and the output signal of the delay gate 7. |
