| 摘要 |
WRITE SHARED CACHE CIRCUIT FOR MULTIPROCESSOR SYSTEM A "write-shared" cache circuit for multiprocessor systems maintains data consistency throughout the system and eliminates non-essential bus accesses by utilizing additional bus lines between caches of the system and by utilizing additional logic in order to enhance the intercache communication. Data is only written through to the system bus when the data is labeled "shared". A writemiss is read only once on the system bus in an "invalidate" cycle, and then it is written only to the requesting cache. |
