| 摘要 |
The circuit includes an input/output buffer (1) for buffering inputted data and for outputting the inputted data through an external common bus. A second buffer (10) buffers various data in accordance with control signals (C2-C6), and a third buffer (20) buffers various data in accordance with control signals (C7-C13). An operation status display signal generating section (40) generates signals to display the various operation status of the system. A control signal generating section (50) generates the control signals (C1-C20) for controlling the three buffers (1)(10)(20). With the circuit, the control signals are separated, and therefore, the operation becomes simpler.
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