发明名称 DIGITAL SIGNAL PROCESSOR
摘要 <p>PURPOSE:To synchronize an internal digital communication clock signal with an external clock signal by sending a digital signal from an A/D converter means to a digital signal processing means synchronously with a communication clock signal from a clock generating means. CONSTITUTION:A clock oscillation block 101 generating an internal communication clock signal is provided on the inside of a 1-chip digital signal processor 100. Moreover, a digital input interface block 140 is provided which receives the internal communication clock or an external communication clock and sends a digital signal from an internal A/D converter block 110 or an external digital signal to a digital signal processing block 120 synchronously with the internal communication block or the external communication clock to the processing unit 100. Thus, even when the unit 100 acts like a master and an external device acts like a slave and also when the external A/D converter 150 or an external digital signal processor acts like a master and the unit 100 acts like a slave, the digital communication clock signal is synchronized.</p>
申请公布号 JPH04196719(A) 申请公布日期 1992.07.16
申请号 JP19900328644 申请日期 1990.11.27
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NISHI YOSHIO
分类号 G06F3/05;G06F1/12;H03H17/00;H03H17/02;H03M1/12 主分类号 G06F3/05
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