发明名称 VERBINDUNGSKONTAKTE ZWISCHEN SUBSTRATEN UND VERFAHREN ZUR HERSTELLUNG DERSELBEN.
摘要 PCT No. PCT/JP86/00364 Sec. 371 Date Feb. 19, 1987 Sec. 102(e) Date Feb. 19, 1987 PCT Filed Jul. 16, 1986 PCT Pub. No. WO87/00686 PCT Pub. Date Jan. 29, 1987.A stack layer structure is formed wherein solderable metal layers are provided at least at two ends thereof, and at least a metal layer for preventing the diffusion of solder is inserted between the two metal layers. In an interboard connection terminal and a method of manufacturing the same, a pair of solder bumps are fixed to be in contact with the two surfaces of the resultant stack layer structure.
申请公布号 DE3685647(D1) 申请公布日期 1992.07.16
申请号 DE19863685647 申请日期 1986.07.16
申请人 发明人
分类号 H01L21/60;H01L23/48;H01L23/485;H01L23/538;H05K1/03;H05K1/18;H05K3/34;H05K3/40 主分类号 H01L21/60
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