Masterslice chip cell providing a plurality of logic types.

摘要

Cell (1) for a masterslice chip providing three separate logic families comprises a plurality of discrete elements including current source (T9,T10) and emitter follower transistors (T11,T12), capacitors (C1,C2) and multitapped resistors (R1-R9), each connected to studs via corresponding contacts. Three channels are defined for wiring each cell to form differential cascode current switch, half current switch and current switch emitter follower logic. The cell also allows wiring to form converters to convert between logic families thereby allowing the masterslice chip any or all of the three logic families on the chip to optimize overall chip performance. <IMAGE>