发明名称 CLOCK REGENERATING CIRCUIT
摘要 PURPOSE:To deal with even input signals different in magnitude of time variation from one another by switching to a highly stable PLL from an input signal having a considerable time variation in magnitude. CONSTITUTION:With the aid of a changeover signal from an input terminal 23, a changeover circuit 22 outputs a synchronous circuit signal to a phase compare circuit 27 when an input signal is a video signal with a considerable magnitude of time variation, or to a phase compare circuit 24 when the input signal is a computer signal with a less magnitude of time variation. Then, by setting a control range of a voltage control oscillating circuit 28 narrower than that of a voltage controlled oscillator circuit 25 at a particular free oscillating frequency, stability can be increased for a video signal with a considerable magnitude of time variation.
申请公布号 JPH04183119(A) 申请公布日期 1992.06.30
申请号 JP19900313538 申请日期 1990.11.19
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TAKATORI MASAHIRO
分类号 H03L7/10 主分类号 H03L7/10
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