Data stream smoothing using a FIFO memory

摘要

A data stream smoothing circuit wherein a FIFO memory receives data from the DRAM, and a memory status circuit provides a memory-full status signal when the FIFO memory contains a selected amount of data from the DRAM. A refresh timer generates a refresh request signal whenever DRAM refresh should be performed. When the refresh request signal is generated, a refresh control circuit refreshes a row of data in the DRAM upon occurrence of the next memory-full status signal.