| 摘要 |
<p>A thin film field effect transistor manufactured using a cladding technique wherein parasitic capacities of the source (24) and drain (12, 15) with respect to the ground are low and a substrate biasing effect is low. The vertical channel field effect transistor comprises a substrate (10), an insulating layer (16) formed on the substrate, and a semiconductor layer formed on the substrate in the insulating layer. The semiconductor layer has one of a source (19) and a drain (12) and an electrode (24, 15) for the one of the source and drain formed at a lower portion thereof while the other of the source and drain and another electrode for the other of the source and drain are formed at an upper portion of the semiconductor layer. The semiconductor layer further has a groove (20) formed therein, and a gate electrode (25) formed in the groove to fill up the same. Several processes of manufacturing such vertical channel field effect transistor are also disclosed. <IMAGE></p> |
