发明名称 LOGIC CIRCUIT
摘要 PURPOSE:To suppress spike noise and to prevent the malfunction of a D--flip-flop by setting a larger delay quantity than a shift of time between signals each applied to a first and a second input terminals to a delay circuit. CONSTITUTION:Levels of an input signal inputted to an input terminal 1 and an input signal applied to an input terminal 2 are inputted with a shift of time T1, therefore, to an output of an EXNOR 3, a spike noise is outputted for the time T1. A signal obtained by delaying the output of the EXNOR 3 by T2 through a delay circuit 4, and a signal applied to the input terminal 1 and an input terminal 2 are inputted to an AND 5. In such a case, the output signal outputted from an output terminal 6 is T2>T1, therefore, even if the level of a signal each applied to the input terminal 1 and the input terminal 2 is varied with a shift of the time T1, spike noise is not generated.
申请公布号 JPH04154316(A) 申请公布日期 1992.05.27
申请号 JP19900279917 申请日期 1990.10.18
申请人 NEC CORP;NEC ENG LTD 发明人 HOKIMOTO TAKEHIRO;SAITO MASAAKI
分类号 H03K19/003;H03K5/01;H03K5/1252;H03K19/20 主分类号 H03K19/003
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