| 摘要 |
A CMOS inverter composed of series connected p-channel and n-channel MOS FETs (Tp, Tn) of which gate electrodes (G), drain contact electrodes (Dp, Dn), and voltage source lines (Vcc, Vss) are arranged on different insulation layers (6, 11) stacked on each other. The drain contact electrodes are formed by a conductor (101; N1, N2...; N21, N31... ) including a silicide of high melting point metal such as tungsten or molybdenum. They are coated by an insulation layer (11) over which the voltage source lines (Vcc, Vss) and signal lines for transferring an output to a succeeding stage are arranged. By doing so, the device area is decreased, and the substrate (1) can be reflowed to smooth the surface of the insulator to prevent disconnection of wirings. |
