发明名称
摘要 PURPOSE:To execute optimum control corresponding to a transmission speed by controlling a flat characteristic equalizing circuit by an output obtained by reading out an ROM. CONSTITUTION:A reference voltage V and an equalizing output OUT are compared by a peak value detecting circuit PD, its magnitude is decided, and the continuity of its result is detected by a pulse controlling circuit PC. Subsequently, a pulse from the circuit PC is counted by a counting circuit CNT, and a counting value corresponding to the gain required for a flat characteristic equalizing circuit FEQ and an inclined characteristic equalizing circuit SEQ is obtained. An output of this circuit CNT becomes an address for an ROM1 and an ROM2. In this way, optimum control corresponding to a transmission speed is attained immediately by controlling the characteristic equalizing circuit by an output obtained by reading out the ROM1.
申请公布号 JPH0427735(B2) 申请公布日期 1992.05.12
申请号 JP19830035456 申请日期 1983.03.04
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KK 发明人 TAKADA AKIHIKO;TANIGUCHI KYOSHI;NAKAJO TAKAFUMI;KIMURA TADAKATSU;ISHIKAWA MASAYUKI
分类号 H04B3/04;H03H11/02;H03H11/04;H04B3/14 主分类号 H04B3/04
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