In a semiconductor memory device including word lines (WL) and bit lines (BL), a regular pattern circuit area comprising elements regularly arranged in line with the word lines and/or the bit lines is divided into a plurality of blocks (1-1, 1-2). Provided between the divided blocks are irregular or peripheral circuit areas (2). Provided outside of the divided blocks are pads (P1 to P16).
申请公布号
DE3485625(D1)
申请公布日期
1992.05.07
申请号
DE19843485625
申请日期
1984.06.28
申请人
FUJITSU LTD., KAWASAKI, KANAGAWA, JP
发明人
TAKEMAE, YOSHIHIRO, TOKYO 107, JP;NAKANO, TOMIO, KAWASAKI-SHI KANAGAWA 213, JP;SATO, KIMIAKI, TOKYO 106, JP